The present invention relates in general to software engineering and, more particularly, to a method of distributed cell characterizations executed by a computer program.
Standard cells are circuits which provide specific, pre-defined functionality for chip designers. When used as building blocks for more complex systems such as microprocessors, the cells and the larger circuits built from the cells must be fully simulated with a circuit simulator such as SPICE prior to fabrication. The computer simulation is a useful step during the design of an electronic circuit to test the various features before a physical embodiment is built. The circuit may be mathematically modeled in the computer simulator whereby the design parameters may be verified or manipulated to work out the inevitable problems associated with different embodiments before proceeding with the cost and effort of building an actual model.
Timing and power characteristics--that is, how quickly the circuit can be cycled and how many watts are consumed during active and idle modes--are primary concerns and must be evaluated for a range of operating temperatures, supply voltages, etc. Because SPICE simulation time grows more than linearly with circuit size, full analog simulations of large semi-custom designs are extraordinarily time-consuming jobs. Each may take many hours to complete even on modern mainframe and mini-supercomputer systems.
Entice is a cell characterization system that approximates analog methods to deliver much shorter solution times and higher throughput on such simulation jobs. Instead of performing a sequential simulation of the complete design, Entice performs smaller simulations of each design's building blocks in one or more workstations. The performance of the complete design is then approximated by forming sums along those components. The total timing delay, for instance, is approximately equal to the sum of the timing delays along the longest path in the overall design. For power, total consumption is approximately equal to the sum of the power consumed by all of the parts.
The bottleneck in cell characterization is the circuit simulation, where each cell in a library is simulated over a range of parameters (input edge rate, output loading, supply voltage, temperature, etc.) to obtain delay parameter relationships. For an average library of say one hundred cells, the number of simulations frequently runs into the tens of thousands.
Hence, a need exists to reduce simulation time as cells and circuits grow more complex.